ceClub: Look-Ahead Clock Gating

Shmuel Wimer (Bar-Ilan University)
Wednesday, 23.4.2014, 11:30
EE Meyer Building 861

Clock gating is very useful for reducing the power consumed by digital systems. Three gating methods are known: synthesis-based, data-driven and auto-gated FFs (AGFF). We present a novel method called Look-Ahead Clock Gating (LACG), which combines all the three. LACG computes the clock enabling signals of each FF one cycle ahead of time, based on the present cycle data of those FFs on which it depends. It avoids the tight timing constraints of AGFF and data-driven by allotting a full clock cycle for the computation of the enabling signals and their propagation. A closed-form model characterizing the power saving per FF is presented. The model implies a breakeven curve, dividing the FFs space into two regions of positive and negative gating return on investment. While the majority of the FFs fall in the positive region and hence should be gated, those falling in the negative region should not. Experimentation on industry-scale data showed 23% reduction of the clock power, on top of other gating methods.

Shmuel Wimer is an Associate Professor with the Engineering Faculty of Bar-Ilan University and a visiting Associate Professor with the EE Dept. of the Technion. He received M.Sc. in mathematics from Tel-Aviv University, and D.Sc. in EE from the Technion. Prior to joining the academia on 2009 he worked for 32 years at the industry for Intel, IBM, National Semiconductors and the Israeli Aerospace Industry. He is interested in optimization of VLSI circuits and systems and in combinatorial optimization.

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